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PALCE20V8
Flash-Erasable Reprogrammable CMOS PAL(R) Device
Features
* Active pull-up on data input pins * Low power version (20V8L) -- 55 mA max. commercial (15, 25 ns) -- 65 mA max. military/industrial (15, 25 ns) * Standard version has low power -- 90 mA max. commercial (15, 25 ns) -- 115 mA max. commercial (10 ns) -- 130 mA max. military/industrial (15, 25 ns) * CMOS Flash technology for electrical erasability and reprogrammability * User-programmable macrocell -- Output polarity control -- Individually selectable for registered or combinatorial operation * QSOP package available -- 10, 15, and 25 ns com'l version -- 15, and 25 ns military/industrial versions * High reliability -- Proven Flash technology -- 100% programming and functional testing
Functional Description
The Cypress PALCE20V8 is a CMOS Flash Erasable second-generation programmable array logic device. It is implemented with the familiar sum-of-product (AND-OR) logic structure and the programmable macrocell. The PALCE20V8 is executed in a 24-pin 300-mil molded DIP, a 300-mil cerdip, a 28-lead square ceramic leadless chip carrier, a 28-lead square plastic leaded chip carrier, and a 24-lead quarter size outline. The device provides up to 20 inputs and 8 outputs. The PALCE20V8 can be electrically erased and reprogrammed. The programmable macrocell enables the device to function as a superset to the familiar 24-pin PLDs such as 20L8, 20R8, 20R6, 20R4.
Logic Block Diagram (PDIP/CDIP/QSOP)
GND 12 I10 11 I9 10 I8 9 I7 8 I6 7 I5 6 I4 5 I3 4 I2 3 I1 2 CLK/I0 1
PROGRAMMABLE AND ARRAY (64 x 40) 8 8 8 8 8 8 8 8
MUX
Macrocell
Macrocell
Macrocell
Macrocell
Macrocell
Macrocell
Macrocell
Macrocell MUX
13 OE/I11
14 I12
15 I/O0
16 I/O1
17 I/O2
18 I/O3
19 I/O4
20 I/O5
21 I/O6
22 I/O7
23 I13
24 VCC
Cypress Semiconductor Corporation Document #: 38-03026 Rev. *B
*
3901 North First Street
*
San Jose, CA 95134
* 408-943-2600 Revised April 19, 2004
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Pin Configuration
DIP/QSOP Top View
CLK/I0 I1 I2 I3 I4 I5 I6 I7 I8 I9 I10 GND 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 VCC I13 I/O7 I/O6 I/O5 I/O4 I/O3 I/O2 I/O1 I/O0 I12 OE/I11
PALCE20V8
PLCC/LCC Top View
I2 I1 CLK/I 0 NC VCC I13 I/O7 4 3 2 1 2827 26 I3 I4 I5 NC I6 I7 I8 5 6 7 8 9 10 11 25 24 23 22 21 20 19 I/O6 I/O5 I/O4 NC I/O3 I/O2 I/O1 121314 1516 1718
Selection Guide
tPD ns Generic Part Number PALCE20V8-5 PALCE20V8-7 PALCE20V8-10 PALCE20V8-15 PALCE20V8-25 PALCE20V8L-15 PALCE20V8L-25 Com'l/Ind 5 7.5 10 15 25 15 25 10 15 25 15 25 Mil 3 7 10 12 15 12 15 10 12 20 12 20 tS ns Com'l/Ind Mil 4 5 7 10 12 10 12 10 12 20 12 20 tCO ns Com'l/Ind Mil 115 115 115 90 90 55 55 130 130 130 65 65 ICC mA Com'l Mil/Ind
Shaded areas contain preliminary information.
Document #: 38-03026 Rev. *B
I9 I10 GND NC OE/I 11 I12 I/O0
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Functional Description
The PALCE20V8 features 8 product terms per output and 40 input terms into the AND array. The first product term in a macrocell can be used either as an internal output enable control or as a data product term. There are a total of 18 architecture bits in the PALCE20V8 macrocell; two are global bits that apply to all macrocells and 16 that apply locally, two bits per macrocell. The architecture bits determine whether the macrocell functions as a register or combinatorial with inverting or noninverting output. The output enable control can come from an external pin or internally from a product term. The output can also be permanently enabled, functioning as a dedicated output or permanently disabled, functioning as a dedicated input. Feedback paths are selectable from either the input/output pin associated with the macrocell, the input/output pin associated with an adjacent pin, or from the macrocell register itself. Power-Up Reset All registers in the PALCE20V8 power-up to a logic LOW for predictable system initialization. For each register, the associated output pin will be HIGH due to active-LOW outputs. Electronic Signature
PALCE20V8
An electronic signature word is provided in the PALCE20V8 that consists of 64 bits of programmable memory that can contain user-defined data. Security Bit A security bit is provided that defeats the readback of the internal programmed pattern when the bit is programmed. Low Power The Cypress PALCE20V8 provides low-power operation through the use of CMOS technology, and increased testability with Flash reprogrammability. Product Term Disable Product Term Disable (PTD) fuses are included for each product term. The PTD fuses allow each product term to be individually disabled. Input and I/O Pin Pull-Ups The PALCE20V8 input and I/O pins have built-in active pull-ups that will float unused inputs and I/Os to an active HIGH state (logical 1). All unused inputs and three-stated I/O pins should be connected to another active input, VCC, or Ground to improve noise immunity and reduce ICC.
Configuration Table
CG0 0 0 1 1 1 CG1 1 1 0 0 1 CL0x 0 1 0 1 1 Cell Configuration Registered Output Combinatorial I/O Combinatorial Output Input Combinatorial I/O Devices Emulated Registered Med PALs Registered Med PALs Small PALs Small PALs 20L8 only
Macrocell
OE VCC 0X 10 11 10 00 01 To Adjacent Macrocell
11
CG1
CL0x 11 0X D Q Q 10 11 0X CG1 for pin 16 to 21 (DIP) CG0 for pin 15 and 22 (DIP) CL0x 10
I/Ox
VCC CLK
CL1x
From Adjacent Pin
Document #: 38-03026 Rev. *B
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Maximum Ratings
(Above which the useful life may be impaired. For user guidelines, not tested.) Storage Temperature ..................................... -65C to +150C Ambient Temperature with Power Applied.................................................. -55C to +125C Supply Voltage to Ground Potential (Pin 24 to Pin 12).................................................-0.5V to +7.0V DC Voltage Applied to Outputs in High-Z State .....................................................-0.5V to +7.0V
PALCE20V8
DC Input Voltage ................................................. -0.5V to +7.0V Output Current into Outputs (LOW)............................. 24 mA DC Programming Voltage............................................. 12.5V Latch-up Current...................................................... >200 mA
Operating Range[1]
Range Commercial Industrial Military[2] Ambient Temperature 0C to +75C -40C to +85C -55C to +125C VCC 5V 5% 5V 10% 5V 10%
Electrical Characteristics Over the Operating Range[3]
Parameter VOH VOL VIH VIL IIH IIL[6] ISC ICC
[5]
Description Output HIGH Voltage Output LOW Voltage Input HIGH Level Input LOW Level Input or I/O HIGH Leakage Current Input or I/O LOW Leakage Current Operating Power Supply Current VCC = Min., VIN = VIH or VIL VCC = Min., VIN = VIH or VIL
Test Conditions IOH = -3.2 mA IOH = -2 mA IOL = 24 mA IOL = 12 mA Com'l Mil/Ind Com'l Mil/Ind
Min. 2.4
Max.
Unit V
0.5 2.0 -0.5 0.8 10 -100 -30 -150 115 90 55
V V V A A mA mA mA mA mA mA
Guaranteed Input Logical HIGH Voltage for All Inputs[4] Guaranteed Input Logical LOW Voltage for All 3.5V < VIN < VCC 0V < VIN < VIN (Max.) Inputs[4]
Output Short Circuit Current VCC = Max., VOUT = 0.5V[7,8] VCC = Max., VIL = 0V, VIH = 3V, Output Open, f = 15 MHz (counter) 5, 7, 10 ns 15, 25 ns 15L, 25L ns 10, 15, 25 ns 15L, 25L ns Mil/Ind Mil/Ind Com'l
130 65
Capacitance[8]
Parameter CIN COUT Description Input Capacitance Output Capacitance Test Conditions VIN = 2.0V @ f = 1 MHz VOUT = 2.0V @ f = 1 MHz Typ. 5 5 Unit pF pF
Endurance Characteristics[8]
Parameter N Description Minimum Reprogramming Cycles Test Conditions Normal Programming Conditions Min. 100 Max. Unit Cycles
Notes: 1. The Voltage on any input or I/O pin cannot exceed the power pin during power-up. 2. TA is the "instant on" case temperature. 3. See the last page of this specification for Group A subgroup testing information. 4. These are absolute values with respect to device ground. All overshoots due to system or tester noise are included. 5. VIL (Min.) is equal to -3.0V for pulse durations less than 20 ns. 6. The leakage current is due to the internal pull-up resistor on all pins. 7. Not more than one output should be tested at a time. Duration of the short circuit should not be more than one second. VOUT = 0.5V has been chosen to avoid test problems caused by tester ground degradation. 8. Tested initially and after any design or process changes that may affect these parameters.
Document #: 38-03026 Rev. *B
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AC Test Loads and Waveforms
ALL INPUT PULSES 3.0V 90% GND 2 ns 10% 90% 10% 2 ns
PALCE20V8
5V
S1 R1 OUTPUT R2 CL TEST POINT
Commercial Specification tPD, tCO tPZX, tEA tPXZ, tER Closed Z H: Open Z L: Closed H Z: Open L Z: Closed 5 pF S1 CL 50 pF R1 200 R2 390 R1
Military R2 750 Measured Output Value 1.5V 1.5V H Z: VOH - 0.5V L Z: VOL + 0.5V 390
Commercial and Industrial Switching Characteristics [3]
20V8-5 Parameter tPD tPZX tPXZ tEA tER tCO tS tH tP Description Input to Output Propagation Delay[9] OE to Output Enable OE to Output Disable Input to Output Enable Delay[8] Input to Output Disable Delay[8,10] Clock to Output Delay[9] Input or Feedback Set-up Time Input Hold Time External Clock Period (tCO + tS) 1 3 0 7 Min. 1 Max. 5 5 5 6 6 4 1 7 0 12 20V8-7 Min. 1 Max. 7.5 6 6 9 9 5 1 10 0 17 20V8-10 Min. 1 Max. 10 10 10 10 10 7 1 12 0 22 20V8-15 Min. 1 Max. 15 15 15 15 15 10 1 15 0 27 20V8-25 Min. 1 Max. 25 20 20 25 25 12 Unit ns ns ns ns ns ns ns ns ns
Shaded areas contain preliminary information. Notes: 9. Min. times are tested initially and after any design or process changes that may affect these parameters. 10. This parameter is measured as the time after OE pin or internal disable input disables or enables the output pin. This delay is measured to the point at which a previous HIGH level has fallen to 0.5 volts below VOH min. or a previous LOW level has risen to 0.5 volts above VOL max. 11. This specification indicates the guaranteed maximum frequency at which a state machine configuration with external feedback can operate. 12. This specification indicates the guaranteed maximum frequency at which the device can operate in data path mode. 13. This specification indicates the guaranteed maximum frequency at which a state machine configuration with internal only feedback can operate. 14. This parameter is calculated from the clock period at fMAX internal (1/fMAX3) as measured (see Note 7 above) minus tS.
Document #: 38-03026 Rev. *B
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Commercial and Industrial Switching Characteristics (continued)[3]
20V8-5 Parameter tWH tWL fMAX1 fMAX2 fMAX3 tCF tPR Description Clock Width HIGH
[8]
PALCE20V8
20V8-15 Min. 8 8 45.5 62.5 50 6 8 1 1 Max. 20V8-25 Min. 12 12 37 41.6 40 10 Max. Unit ns ns MHz MHz MHz ns s
20V8-7 Min. 5 5 83 100 100 Max.
20V8-10 Min. 8 8 58 62.5 62.5 Max.
Min. 3 3 143
Max.
Clock Width LOW[8] External Maximum Frequency (1/(tCO + tS))[8,11]
Data Path Maximum 166.6 Frequency (1/(tWH + tWL))[8, 12] Internal Feedback Maximum Frequency (1/(tCF + tS))[8,13] Register Clock to Feedback Input[8, 14] Power-Up Reset Time[8] 1 166.6 3
3 1 1
Military Switching Characteristics[3]
20V8-10 Parameter tPD tPZX tPXZ tEA tER tCO tS tH tP tWH tWL fMAX1 fMAX2 fMAX3 tCF tPR Description Input to Output Propagation Delay[9] OE to Output Enable OE to Output Disable Input to Output Enable Clock to Output Input Hold Time External Clock Period (tCO + tS) Clock Width HIGH[8] Clock Width LOW[8] External Maximum Frequency (1/(tCO + tS)[8,11] Data Path Maximum Frequency (1/(tWH + tWL))[8, 12 ] Internal Feedback Maximum Frequency (1/(tCF + tS))[8,13] Register Clock to Feedback Input[8, 14] Power-Up Reset Time[8] 1 Delay[8] 1 10 0 20 8 8 50 62.5 62.5 6 1 Input to Output Disable Delay[8,10] Delay[9] Input or Feedback Set-Up Time Min. 1 Max. 10 10 10 10 10 10 1 12 0 24 10 10 41.7 50 50 8 1 20V8-15 Min. 1 Max. 15 15 15 15 15 12 1 20 0 40 15 15 25 33.3 33.3 10 20V8-25 Min. 1 Max. 25 20 20 25 25 20 Unit ns ns ns ns ns ns ns ns ns ns ns MHz MHz MHz ns s
Document #: 38-03026 Rev. *B
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Switching Waveform
INPUTS, I/O, REGISTERED FEEDBACK tS CP t CO REGISTERED OUTPUTS t PD COMBINATORIAL OUTPUTS tPXZ, tER
[11]
PALCE20V8
tH
t WH
t WL
tP
tPXZ, tER[11]
tEA, tPZX[11]
[11] tEA, tPZX
Power-Up Reset Waveform
POWER SUPPLY VOLTAGE REGISTERED ACTIVE LOW OUTPUTS CLOCK tPR MAX = 1 s t WL 10% 90% t PR VCC
tS
Document #: 38-03026 Rev. *B
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Functional Logic Diagram for PALCE20V8
PIN NUMBERS DIP (PLCC) PACKAGE
PALCE20V8
1 (2)
0 4 8 12 16 20 24 28 32 32 PTD
PIN NUMBERS DIP (PLCC)PACKAGE 1 0 CG0 0
2 (3)
23 (27)
MC7 CL1=2560 CL0=2632
22 (26)
280
3 (4)
320
MC6 CL1=2561 CL0=2633
21 (25)
600
4 (5)
640
MC5 CL1=2562 CL0=2634
20 (24)
920
5 (6)
960
MC4 CL1=2563 CL0=2635
19 (23)
1240
6 (7)
1280
MC3 CL1=2564 CL0=2636
18 (21)
1560
7 (9)
1600
MC2 CL1=2565 CL0=2637
17 (20)
1880
8 (10)
1920
MC1 CL1=2566 CL0=2638
16 (19)
2200
9 (11)
2240
MC0 CL1=2567 CL0=2639
15 (18)
2520
10 (12) 11 (13)
CG0 0 1
14 (17) 13 (16)
ELECTRONIC SIGNATURE ROW 2568 BYTE7 2569 . . . BYTE6 . . . . . . 2630 . . . BYTE1 2631 BYTE0 CG0=2704 CG1=2705
MSB LSB
Document #: 38-03026 Rev. *B
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Ordering Information for PALCE20V8
ICC (mA) 115 115 115 tPD (ns) 5 7.5 10 tS (ns) 3 7 10 tCO (ns) 4 5 7 Ordering Code PALCE20V8-5JC PALCE20V8-7JC PALCE20V8-7PC PALCE20V8-10JC PALCE20V8-10PC PALCE20V8-10QC 130 10 10 10 PALCE20V8-10JI PALCE20V8-10PI PALCE20V8-10DMB PALCE20V8-10LMB 90 15 12 10 PALCE20V8-15JC PALCE20V8-15PC PALCE20V8-15QC 130 15 12 12 PALCE20V8-15JI PALCE20V8-15PI PALCE20V8-15QI PALCE20V8-15DMB PALCE20V8-15LMB 90 25 15 12 PALCE20V8-25JC PALCE20V8-25PC PALCE20V8-25QC 130 25 20 20 PALCE20V8-25JI PALCE20V8-25PI PALCE20V8-25QI PALCE20V8-25DMB PALCE20V8-25LMB
Shaded areas contain preliminary information.
PALCE20V8
Package Name J64 J64 P13 J64 P13 Q13 J64 P13 D14 L64 J64 P13 Q13 J64 P13 Q13 D14 L64 J64 P13 Q13 J64 P13 Q13 D14 L64
Package Type 28-Lead Plastic Leaded Chip Carrier 28-Lead Plastic Leaded Chip Carrier 24-Lead (300-Mil) Molded DIP 28-Lead Plastic Leaded Chip Carrier 24-Lead (300-Mil) Molded DIP 24-Lead Quarter-Size Outline 28-Lead Plastic Leaded Chip Carrier 24-Lead (300-Mil) Molded DIP 24-Lead (300-Mil) CerDIP 28-Pin Square Leadless Chip Carrier 28-Lead Plastic Leaded Chip Carrier 24-Lead (300-Mil) Molded DIP 24-Lead Quarter-Size Outline 28-Lead Plastic Leaded Chip Carrier 24-Lead (300-Mil) Molded DIP 24-Lead Quarter-Size Outline 24-Lead (300-Mil) CerDIP 28-Pin Square Leadless Chip Carrier 28-Lead Plastic Leaded Chip Carrier 24-Lead (300-Mil) Molded DIP 24-Lead Quarter-Size Outline 28-Lead Plastic Leaded Chip Carrier 24-Lead (300-Mil) Molded DIP 24-Lead Quarter-Size Outline 24-Lead (300-Mil) CerDIP 28-Pin Square Leadless Chip Carrier
Operating Range Commercial Commercial
Industrial Military Commercial
Industrial
Military Commercial
Industrial
Military
Ordering Information for PALCE20V8L
ICC (mA) 55 tPD (ns) 15 tS (ns) 12 tCO (ns) 10 Ordering Code PALCE20V8L-15JC PALCE20V8L-15PC PALCE20V8L-15QC 65 15 12 12 PALCE20V8L-15JI PALCE20V8L-15PI PALCE20V8L-15QI PALCE20V8L-15DMB PALCE20V8L-15LMB 55 25 15 12 PALCE20V8L-25JC PALCE20V8L-25PC PALCE20V8L-25QC Package Name J64 P13 Q13 J64 P13 Q13 D14 L64 J64 P13 Q13 Package Type 28-Lead Plastic Leaded Chip Carrier 24-Lead (300-Mil) Molded DIP 24-Lead Quarter-Size Outline 28-Lead Plastic Leaded Chip Carrier 24-Lead (300-Mil) Molded DIP 24-Lead Quarter-Size Outline 24-Lead (300-Mil) CerDIP 28-Pin Square Leadless Chip Carrier 28-Lead Plastic Leaded Chip Carrier 24-Lead (300-Mil) Molded DIP 24-Lead Quarter-Size Outline Commercial Military Industrial Operating Range Commercial
Document #: 38-03026 Rev. *B
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Ordering Information for PALCE20V8L (continued)
ICC (mA) 65 tPD (ns) 25 tS (ns) 20 tCO (ns) 20 Ordering Code PALCE20V8L-25JI PALCE20V8L-25PI PALCE20V8L-25QI PALCE20V8L-25DMB PALCE20V8L-25LMB Package Name J64 P13 Q13 D14 L64 Package Type
PALCE20V8
Operating Range Industrial
28-Lead Plastic Leaded Chip Carrier 24-Lead (300-Mil) Molded DIP 24-Lead Quarter-Size Outline 24-Lead (300-Mil) CerDIP 28-Pin Square Leadless Chip Carrier
Military
Document #: 38-03026 Rev. *B
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MILITARY SPECIFICATIONS Group Subgroup Testing DC Characteristics
Parameter VOH VOL VIH VIL IIX IOZ ICC 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 Subgroups
PALCE20V8
Switching Characteristics
Parameter tPD tCO tS tH Subgroups 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11
Package Diagrams
24-Lead (300-Mil) CerDIP D14
MIL-STD-1835 D- 9 Config.A
51-80031-**
Document #: 38-03026 Rev. *B
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Package Diagrams (continued)
28-Lead Plastic Leaded Chip Carrier J64
PALCE20V8
51-85001-*A
28-Square Leadless Chip Carrier L64
MIL-STD-1835 C-4
51-80051-**
Document #: 38-03026 Rev. *B
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Package Diagrams (continued)
24-Lead (300-Mil) PDIP P13
PALCE20V8
51-85013-*B
24-Lead Quarter Size Outline Q13
51-85055-B
Ultra37000 is a trademark of Cypress Semiconductor Corporation. PAL is a registered trademark of Advanced Micro Devices, Inc. All products and company names mentioned in this document may be the trademarks of their respective holders.
Document #: 38-03026 Rev. *B
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(c) Cypress Semiconductor Corporation, 2004. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
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Document History Page
Document Title: PALCE20V8 Flash-Erasable Reprogrammable CMOS PAL(R) Device Document Number: 38-03026 REV. ** *A *B ECN NO. 106371 122231 213375 Issue Date 07/11/01 12/28/02 See ECN Orig. of Change SZV RBI FSG Description of Change Changed from Spec Number: 38-00367 to 38-03026
PALCE20V8
Added power-up requirements to Operating Range Information Added note to title page: "Use Ultra37000 For All New Designs"
Document #: 38-03026 Rev. *B
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